\doxysection{SPI\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_s_p_i___type_def}{}\label{struct_s_p_i___type_def}\index{SPI\_TypeDef@{SPI\_TypeDef}}


Serial Peripheral Interface.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a38cb89a872e456e6ecd29b6c71d85600}{CR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5}{IFCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a2e297cd0cbca5b9878dab319aee83ae5}{RESERVED0}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a519806144e513633e6a0093fd554756f}{TXDR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a6e739471dd1c66b23dd856f4391860ab}{RESERVED1}} \mbox{[}3\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a0339afbc47839f09598f7fb09c242b09}{RXDR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a2021528927d75d06c03dcedb9fc36d51}{RESERVED2}} \mbox{[}3\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a03d6f39b695fb8e316e97c8a089cd46b}{CRCPOLY}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a9fffd568c7ff1da72b24c45c62566abd}{TXCRC}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_aa3d580e3aa375dd3e6c1a3331e819300}{RXCRC}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a189a6e7526779ec981cd411bc4bd3a51}{UDRDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2\+SCFGR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Serial Peripheral Interface. 

\label{doc-variable-members}
\Hypertarget{struct_s_p_i___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}\index{SPI\_TypeDef@{SPI\_TypeDef}!CFG1@{CFG1}}
\index{CFG1@{CFG1}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFG1}{CFG1}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+CFG1}

SPI Configuration register 1, Address offset\+: 0x08 \Hypertarget{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}\index{SPI\_TypeDef@{SPI\_TypeDef}!CFG2@{CFG2}}
\index{CFG2@{CFG2}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFG2}{CFG2}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+CFG2}

SPI Configuration register 2, Address offset\+: 0x0C \Hypertarget{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}\index{SPI\_TypeDef@{SPI\_TypeDef}!CR1@{CR1}}
\index{CR1@{CR1}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR1}{CR1}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+CR1}

SPI/\+I2S Control register 1, Address offset\+: 0x00 \Hypertarget{struct_s_p_i___type_def_a38cb89a872e456e6ecd29b6c71d85600}\index{SPI\_TypeDef@{SPI\_TypeDef}!CR2@{CR2}}
\index{CR2@{CR2}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR2}{CR2}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a38cb89a872e456e6ecd29b6c71d85600} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+CR2}

SPI Control register 2, Address offset\+: 0x04 \Hypertarget{struct_s_p_i___type_def_a03d6f39b695fb8e316e97c8a089cd46b}\index{SPI\_TypeDef@{SPI\_TypeDef}!CRCPOLY@{CRCPOLY}}
\index{CRCPOLY@{CRCPOLY}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CRCPOLY}{CRCPOLY}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a03d6f39b695fb8e316e97c8a089cd46b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+CRCPOLY}

SPI CRC Polynomial register, Address offset\+: 0x40 \Hypertarget{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}\index{SPI\_TypeDef@{SPI\_TypeDef}!I2SCFGR@{I2SCFGR}}
\index{I2SCFGR@{I2SCFGR}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{I2SCFGR}{I2SCFGR}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+I2\+SCFGR}

I2S Configuration register, Address offset\+: 0x50 \Hypertarget{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}\index{SPI\_TypeDef@{SPI\_TypeDef}!IER@{IER}}
\index{IER@{IER}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IER}{IER}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+IER}

SPI/\+I2S Interrupt Enable register, Address offset\+: 0x10 \Hypertarget{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5}\index{SPI\_TypeDef@{SPI\_TypeDef}!IFCR@{IFCR}}
\index{IFCR@{IFCR}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IFCR}{IFCR}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+IFCR}

SPI/\+I2S Interrupt/\+Status flags clear register, Address offset\+: 0x18 \Hypertarget{struct_s_p_i___type_def_a2e297cd0cbca5b9878dab319aee83ae5}\index{SPI\_TypeDef@{SPI\_TypeDef}!RESERVED0@{RESERVED0}}
\index{RESERVED0@{RESERVED0}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED0}{RESERVED0}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a2e297cd0cbca5b9878dab319aee83ae5} 
uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+RESERVED0}

Reserved, 0x1C \Hypertarget{struct_s_p_i___type_def_a6e739471dd1c66b23dd856f4391860ab}\index{SPI\_TypeDef@{SPI\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a6e739471dd1c66b23dd856f4391860ab} 
uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+RESERVED1\mbox{[}3\mbox{]}}

Reserved, 0x24-\/0x2C \Hypertarget{struct_s_p_i___type_def_a2021528927d75d06c03dcedb9fc36d51}\index{SPI\_TypeDef@{SPI\_TypeDef}!RESERVED2@{RESERVED2}}
\index{RESERVED2@{RESERVED2}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED2}{RESERVED2}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a2021528927d75d06c03dcedb9fc36d51} 
uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+RESERVED2\mbox{[}3\mbox{]}}

Reserved, 0x34-\/0x3C \Hypertarget{struct_s_p_i___type_def_aa3d580e3aa375dd3e6c1a3331e819300}\index{SPI\_TypeDef@{SPI\_TypeDef}!RXCRC@{RXCRC}}
\index{RXCRC@{RXCRC}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RXCRC}{RXCRC}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_aa3d580e3aa375dd3e6c1a3331e819300} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+RXCRC}

SPI Receiver CRC register, Address offset\+: 0x48 \Hypertarget{struct_s_p_i___type_def_a0339afbc47839f09598f7fb09c242b09}\index{SPI\_TypeDef@{SPI\_TypeDef}!RXDR@{RXDR}}
\index{RXDR@{RXDR}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RXDR}{RXDR}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a0339afbc47839f09598f7fb09c242b09} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+RXDR}

SPI/\+I2S Receive data register, Address offset\+: 0x30 \Hypertarget{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}\index{SPI\_TypeDef@{SPI\_TypeDef}!SR@{SR}}
\index{SR@{SR}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+SR}

SPI/\+I2S Status register, Address offset\+: 0x14 \Hypertarget{struct_s_p_i___type_def_a9fffd568c7ff1da72b24c45c62566abd}\index{SPI\_TypeDef@{SPI\_TypeDef}!TXCRC@{TXCRC}}
\index{TXCRC@{TXCRC}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TXCRC}{TXCRC}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a9fffd568c7ff1da72b24c45c62566abd} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+TXCRC}

SPI Transmitter CRC register, Address offset\+: 0x44 \Hypertarget{struct_s_p_i___type_def_a519806144e513633e6a0093fd554756f}\index{SPI\_TypeDef@{SPI\_TypeDef}!TXDR@{TXDR}}
\index{TXDR@{TXDR}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TXDR}{TXDR}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a519806144e513633e6a0093fd554756f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+TXDR}

SPI/\+I2S Transmit data register, Address offset\+: 0x20 \Hypertarget{struct_s_p_i___type_def_a189a6e7526779ec981cd411bc4bd3a51}\index{SPI\_TypeDef@{SPI\_TypeDef}!UDRDR@{UDRDR}}
\index{UDRDR@{UDRDR}!SPI\_TypeDef@{SPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{UDRDR}{UDRDR}}
{\footnotesize\ttfamily \label{struct_s_p_i___type_def_a189a6e7526779ec981cd411bc4bd3a51} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPI\+\_\+\+Type\+Def\+::\+UDRDR}

SPI Underrun data register, Address offset\+: 0x4C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
